MQ342-01
Application
Manual
Real Time Clock Module
RTC-4553AC
In pursuit of "Saving" Technology ,Epson electronic device. Our Lineup of semiconductors, Liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings.
NOTICE
* No part of this material may be reproduced or duplicated in any form or any means without the written permission of Seiko Epson. * Seiko Epson reserves the right to make changes to this material without notice. * Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. * Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. * This material of portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of international Trade and industry or other approval from another government agency.
RTC - 4553AC CONTETS 1. Overview..........................................................................................1 2. Block Diagram .................................................................................1 3. Terminal description ........................................................................2
3.1. Terminal connections ........................................................................................ 2 3.2. Terminal functions............................................................................................. 2
4. Absolute maximum ratings...............................................................3 5. Recommended operating conditions................................................3 6. Frequency characteristics................................................................3 7. Electrical characteristics ..................................................................4
7.1. DC, AC Characteristics ..................................................................................... 4
7.1.1. VDD = 5 V........................................................................................................................... 4 7.1.2. VDD = 3 V........................................................................................................................... 5
7.2. Timing Chart ..................................................................................................... 6
8. How to use.......................................................................................7
8.1. Registers........................................................................................................... 7
8.1.1. Register Table ................................................................................................................... 7 8.1.2. Register Bit Functions ....................................................................................................... 8
8.2. Register Description.......................................................................................... 9
8.2.1. Time/Calendar Counter Registers ..................................................................................... 9 8.2.2. Control Registers ............................................................................................................. 10
8.3. How to use...................................................................................................... 12
8.3.1. Data Read ....................................................................................................................... 12 8.3.2. Data Write/Modify ............................................................................................................ 12 8.3.3. Initialize............................................................................................................................ 12 8.3.4. Timing Pulse Output ........................................................................................................ 12 8.3.5. Sample Operation Flow Charts........................................................................................ 13 8.3.6. CS1 and CS0 Operation................................................................................................. 15 8.3.7. System Power Down During Interface Operation ............................................................ 15 8.3.8. Power Supply and CS1 Operation................................................................................... 15 8.3.9. Power-On Reset .............................................................................................................. 16 8.3.10. Power Supply Connection Example .............................................................................. 16 8.3.11. Processing of Non-Existent Data................................................................................... 17 8.3.12. Timing Charts ................................................................................................................ 18
9. External dimensions / Marking layout ............................................21
9.1. External dimensions........................................................................................ 21 9.2. Marking layout................................................................................................. 21
10. Reference Data ...........................................................................22 11. Application notes .........................................................................23
11.1. Notes on handling ......................................................................................... 23 11.2. Notes on packaging ...................................................................................... 23
RTC - 4553AC Real-Time Clock Module
RTC - 4553AC
* Designed for E-mater * Built-in 32.768 kHz quartz crystal allows adjustment- free operation and assures high accuracy * Integrated clock (hours, minutes, seconds) and calendar (year, month, day, day of the week) counter * Automatic leap year compensation until 2099 * Selectable 24-hour/12-hour display mode (with AM/PM indication) * Clock data modification using increment method * Clock data serial output in BCD format * Software controlled 30 second adjustment * Selectable 1/10 Hz or 1024 Hz timing pulse output * Built-in SRAM (30 x 4 bit) * Constant voltage drive realizes low power consumption (1 A Typ.) and minimizes voltage-induced frequency fluctuations * Supports low-voltage operation (3 V)
1. Overview
The RTC-4553 is a very compact real-time clock module with permanent calendar and serial data -6 input/output. The module is designed for E-mater; time accuracy is within 5x10 (0.432 sec./day). It incorporates a heat-resistant 32.768 kHz quartz oscillator. The space saving package allows high-density mounting and facilitates automated production. Besides the clock and calendar functions (comprising all items from years to seconds), the RTC-4553 incorporates also a 30 x 4 bit SRAM and offers other useful features. The use of a CMOS IC makes possible low-voltage, low-power operation, to ensure proper timekeeping also when powered from a backup battery.
2. Block Diagram
32.768 kHz Day of Sec. Min. Hou. week Day Mon. Year
OSC
Counter
TPOUT
Output controller
Control register 1
Control register 2
Control register 3
RAM (120bit)
SOUT SCK SIN CS1 CS0 WR
Input controller
Output controller
Shift controller
Control circuit
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RTC - 4553AC 3. Terminal description
3.1. Terminal connections
RTC - 4553
1. 2. 3. 4. 5. 6. 7. GND #1 WR SIN SCK L1 L2 #7 L3 SOP - 14 pin #8 8. VDD #14 13. 12. 11. 10. 9. SOUT CS1 CS0 L5 L4 14. TPOUT
3.2. Terminal functions
Signal designation Pin No. 1 Input / Output -- Function Power supply negative pin. Connect to ground. Address and data are written at WR = "L". Counter data (second digit to WR ( WRITE enable ) SIN ( Serial input ) SCK ( Serial clock ) L1-L3 L4 , L5 2 I year digit) are written using the incrementing method. Data at the specified address are read at WR = "H". While the address is being set at SIN, the data at SOUT are for the previously specified address. 3 I Serial address and data I/O pin. Serves for address and control register writing for the various counters, and for RAM address and data writing. Serial I/O sync signal input pin. Input a sync signal to this pin to allow address 4 5-7 9, 10 I and data read/write synchronized to this signal. One cycle comprises 8 clocks (4 address clocks + 4 data clocks) -- Test pins reserved for use by Epson. Be sure to leave these pins unconnected. Power supply pin. Connect to a power source. For normal operation and bus VDD 8 -- access, supply 5 V 10% or 3 V 10%. For backup battery operation, provide a voltage of 2 V or higher. See Note 1. CS0 ( Chip select 0 ) CS1 ( Chip select 1 ) SOUT ( Serial output ) TPOUT ( Timing pulse 14 O This pin serves to select the RTC. While CS0 is "L", the microprocessor 11 I can perform register access. While high-impedance state. Connect this pin to the power down detection circuit. If no power down 12 I detection circuit is used, fix the pin at "H" (VDD). When CS1 is "L", SOUT and TPOUT are in the high-impedance state, regardless of CS0 . 13 O Serial address and data output pin. Serves for address and control register readout of the various counters, and for RAM address and data readout. Output pin for 1024 Hz or 1/10 Hz timing pulse, based on internal reference clock. For clock accuracy checking, use 1/10 Hz. CS0 is "H", SOUT is in the
GND
output ) For 1024 Hz, the duty cycle changes once every 10 seconds. Note1 At initial power-on or voltage restoration from an intermediate potential outside of the range where operation is assured (0.3 V to 1.9 V), the power-on reset circuit may not operate normally, leading to possible malfunction. (See section " 8.3.9. Power-On Reset ".) Note2 Be sure to connect a bypass capacitor of 0.1 F or more directly between VDD and GND.
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RTC - 4553AC 4. Absolute maximum ratings
Item
Power supply voltage Input voltage Output voltage Storage temperature Soldering conditions GND=0 V
Symbol
VDD VIN VOUT TSTG TSOL
Condition (pin)
VDD-GND SIN, SCK , WR , CS0 , CS1 SOUT, TPOUT
Stored bare product after unpacking
Min.
-0.3 -0.3 -0.3
Max.
+6.0 VDD+0.3 VDD+0.3
Unit
V
--
+125 C -55 Twice at under +260 C within 10 seconds, or under +230 C within 3 minutes
5. Recommended operating conditions
Item
Power supply voltage Operation temperature
GND=0 V
Symbol
VDD TOPR
Condition
VDD-GND No condensation
Min.
2.7 -30
Typ.
5.0 --
Max.
5.5 +70
Unit
V C
6. Frequency characteristics
Item
Frequency precision Frequency/temperature characteristics Frequency/voltage characteristics Aging Note (1) Frequency tolerance rating applies to VDD = 5.0 V. (At VDD = 3 V, voltage characteristics must be taken into consideration.) (2) Frequency tolerance rating applies at the time of shipment. (3) Design the peripheral circuitry so that power start-up time (tR) is 1.0 s/V tR 1.6 ms/V.
GND=0 V
Symbol
f / fo tOP f/V fa
Condition
Ta = +25 C VDD = 5.0 V AC
Rating
5 0.432 +10 -120 5 5
Unit
x 10
-6
sec. / day x 10 x 10 x 10
-6 -6
Ta = -10 C to +70 C, VDD = 5 V (Referenced at +25 C ) Ta = Fixed, VDD = 2 V to 5.5 V (Referenced at 5 V) Ta = +25 C, VDD = 5 V, First year
-6
/ year
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RTC - 4553AC 7. Electrical characteristics
7.1. DC, AC Characteristics
7.1.1. VDD = 5 V (1) DC Characteristics Item Data retention voltage Symbol VDH IDD1 (normal operation) IDD2 (backup operation) VOH VOL IOZH IOZL VIH VIL IIH IIL Ts Condition -- SCK = 500 kHz -- CS0 = L, CS1 = H -- CS0 = H, CS1 = L VDD - 0.4 -- -2.0 -2.0 4/5 VDD -- -2.0 -2.0 -- -- -- -- -- -- -- -- -- -- -- 0.4 2.0 2.0 -- 1/5 VDD 2.0 2.0 3.0 V A V A s IOH = -400 A IOL = 1.6 mA VOUT = 5.5 V VOUT = 0 V -- -- VIN = 5.5 V VIN = 0 V Ta = +25 C 1.0 3.0 SCK = 0 Hz -- 100 A ( GND=0 V , Ta = -30 C +70 C ) VDD = 5 V 10 % Unit Min. Typ. Max. 2.0 -- 5.5 V
Current consumption
Output voltage Output leak current Input voltage Input current Oscillation startup time (2) AC Characteristics Item SCK frequency SCK "L" time SCK "H" time SCK pause time CS0 setup time CS0 hold time SIN data setup time SIN data hold time WR setup time WR hold time SOUT delay time
Symbol fCLK tWCKL tWCKH tPS tSCS tHCS tSD tHD tSWR tHWR tDS0 tDSZ1 tDSZ2 tDPZ1 tDPZ2
Condition -- -- -- -- -- -- -- -- -- -- CL=100 pF CL=100 pF CL=100 pF CL=100 pF CL=100 pF
( GND=0 V , Ta = -30 C +70 C ) VDD = 5 V 10 % Unit Min. Typ. Max. -- 1.0 1.0 1.0 0 0.5 0.2 0.2 1.0 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 150 -- -- -- -- 500 -- -- -- -- -- -- -- -- -- 500 100 100 100 100 s kHz
Time lag between CS0 , CS1 enable and SOUT output Time lag between CS0 disable and SOUT high Z Time lag between CS1 enable and TPOUT output Time lag between CS1 disable and TPOUT high Z
ns
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7.1.2. VDD = 3 V (1) DC Characteristics Item Data retention voltage Symbol VDH IDD1 (normal operation) IDD2 (backup operation) VOH VOL IOZH IOZL VIH VIL IIH IIL TS Condition -- SCK = 300 kHz -- CS0 = L, CS1 = H -- CS0 = H, CS1 = L VDD-0.4 -- -2.0 -2.0 4/5 VDD -- -2.0 -2.0 -- -- -- -- -- -- -- -- -- -- -- 0.4 2.0 2.0 -- 1/5 VDD 2.0 2.0 3.0 V A V A s IOH = -400 A IOL = 1.2 mA VOUT = 3.3 V VOUT = 0 V -- -- VIN = 3.3 V VIN = 0 V Ta = +25 C 1.0 3.0 SCK = 0 Hz -- 100 A ( GND=0 V , Ta = -30 C +70 C ) VDD = 3 V 10 % Unit Min. Typ. Max. 2.0 -- 3.3 V
Current consumption
Output voltage Output leak current Input voltage Input current Oscillation startup time (2) AC Characteristics Item SCK frequency SCK "L" time SCK "H" time SCK pause time CS0 setup time CS0 hold time SIN data setup time SIN data hold time WR setup time WR hold time SOUT delay time
Symbol fCLK tWCKL tWCKH tPS tSCS tHCS tSD tHD tSWR tHWR tDSO tDSZ1 tDSZ2 tDPZ1 tDPZ2
Condition -- -- -- -- -- -- -- -- -- -- CL=100 pF CL=100 pF CL=100 pF CL=100 pF CL=100 pF
( GND=0 V , Ta = -30 C +70 C ) VDD = 3 V 10 % Unit Min. Typ. Max. -- 1.5 1.5 1.5 0 1.0 0.2 0.2 1.5 1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 300 -- -- -- -- 300 -- -- -- -- -- -- -- -- -- 500 200 200 ns 200 200 s kHz
Time lag between CS0 , CS1 enable and SOUT output Time lag between CS0 disable and SOUT high Z Time lag between CS1 enable and TPOUT output Time lag between CS1 disable and TPOUT high Z
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7.2. Timing Chart
90 %
CS0
10 %
90 % 10 %
SCK
tSCS
tWCKL 1/f CLK
tWCKH
tHCS
90 %
SIN
10 %
tSD
tHD
WR
tSWR tHWR
SOUT
90 % 10 %
tDSZ1
tDSZ2
CS0
90 %
SCK
1
8
1
tps
SCK
10 %
SOUT
tDSO
90 % 10 %
CS1
90 % 10 %
TPOUT
90 % 10 %
tDPZ1
tDPZ2
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RTC - 4553AC 8. How to use
8.1. Registers
8.1.1. Register Table
0
MODE 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Address A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Register A0 designation 0 S1 1 S10 0 MI1 1 MI10 0 H1 1 H10 0 1 0 1 0 1 0 1 0 1 W D1 D10 MO1 MO10 Y1 Y10 CNT 1 CNT 2 CNT 3 D3 S8 0 mi8 0 h8 PM/
AM
0 1 2 3 4 5 6 7 8 9 A B C D E F
D2 S4 S40 mi4 mi40 h4 0 w4 d4 0 mo4 0 y4 y40 30ADJ PONC TEST
0 d8 0 mo8 0 y8 y80 TPS BUSY SYSR
d2 d20 mo2 0 y2 y20 CNTR
MODE 2 (User RAM register 2) Address User RAM register A3 A2 A1 A0 D3 D2 D1 D0 0 0 0 0 0 RA63 RA62 RA61 RA60 RA64 MODE 1 (User RAM register 1) RA68 Address User RAM register RA72 A3 A2 A1 A0 D3 D2 D1 D0 RA76 0 0 0 0 RA3 RA2 RA1 RA0 RA80 RA4 RA84 RA8 Counter control register D1 D0 Register name RA12 RA88 S2 S1 1-second digit counter RA16 RA92 S20 S10 10-second digit counter RA20 RA96 mi2 mi1 1-minute digit counter RA24 RA100 mi20 mi10 10-minute digit counter RA28 RA104 h2 h1 1-hour digit counter RA32 RA108 h20 h10 10-hour digit counter RA36 RA112 RA40 RA116 w2 w1 Day of the week digit counter RA44 MS0
d1 d10 mo1 mo10 y1 y10
12
24/
1-day digit counter 10-day digit counter 1-month digit counter 10-month digit counter 1-year digit counter 10-year digit counter Control register 1 Control register 2 Control register 3
RA48 RA52 RA56 MS0
--
MS1
MS0
* In positive logic, "H" on the data bus corresponds to "1" in the register. "ADDRESS_F" of MODE 1 and MODE 2 is the same as "ADDRESS_F" of MODE 0. Notes (1) Do not set invalid (out of range) data for the time and calendar. Otherwise counting errors may occur. (2) At power-on (before initialization), the data for each bit are cleared. Write the registers to set the values. (3) Always set the D0 bit ( bit) of the control register 2 to "0". (4) When reading the D1 bit (-- bit) of the control register 2, data of this bit are undefined. (5) Always set the D3 bit (TEST bit) of the control register 3 to "0".
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8.1.2. Register Bit Functions
Bit name
Bit marked "0" Second to year digit PM/ AM
Function
Unused bit that cannot be written. Always read as "0". BCD code. Data are written using increment method. "1" indicates PM and "0" indicates AM. This bit can be read also when 24-hour format is selected (24/12=1). (AM: 00:00 to 11:59, PM: 12:00 to 23:59) To be coded as 7-base counter. Example
Data 0 1 2 3 4 5 6
Day of the week digit Year digit User RAM area
Coded day of the week Sun. Mon. Tue. Wed. Thu. Fri. Sat. Automatic leap year compensation up to 2099 30 x 4 bit SRAM Bit for selecting reference signal output TPS bit Frequency (cycle time) waveform.
0 1024 Hz (976.5 s) 1 1/10 Hz (10 s) Note 1/10 Hz is not output for 10 seconds after power-on or system reset (output is "L"). Setting this bit to "1" performs 30 second adjustment. The bit automatically resets when 30 second adjustment is completed (after 76.3 s). Setting this bit to "1" resets the time and calendar counters.
TPS (Timing pulse selection)
30ADJ (30 seconds adjustment) CNTR (Counter reset) 24/ 12
24-hour or 12-hour format selection bit. When set to "1", 24-hour format is used. When set to "0", 12-hour format is used. Used when reading/writing time and calendar counter data. Set to "1" when carry occurs.
BUSY bit 0 1 Mode No carry Carry Meaning Time/calendar counter read/write possible Time/calendar counter read/write prohibited
Busy
At power-on, the power-on-clear function automatically sets this bit to "1". This has the same effect as data initialization. PONC (Power-on-clear detection)
Register Time/calendar counters Control registers User RAM area Data 00- year, 01-month, 01-day, AM 12-hour, 00-minute, 00- second, 0-day of the week All "0" (PONC = "1") Undefined
Bit marked " - " Bit marked " "
When PONC is "1", data must be set. First clear this bit (this can be done by writing "1" to SYSR and then releasing system reset) and then set the time/calendar counters. Cannot be written. When read, the data are undefined. Can be written but must always be set to "0". At SYSR = "1" all logic bits are initialized. The SYSR bit is reset to "0" by causing an up transition of CS0 and a down transition of SCK.
Register Time/calendar counters Control registers User RAM area Data 00- year, 01-month, 01-day, AM 12-hour, 00-minute, 00- second, 0-day of the week All "0" (SYSR = "1") Undefined
SYSR (System reset)
TEST
Epson test bit. Must be set to "0". These 2 bits serve for mode selection.
MS1 0 MS0 0 1 0 1 Mode name Mode 0 Mode 0 Mode 1 Mode 2 Content Time/calendar counters and control registers 1 - 3 Time/calendar counters and control registers 1 - 3 User RAM area (RA0 - RA59) and control register 3 User RAM area (RA60 - RA119) and control register 3
MS0, MS1 (Mode selection)
0 1 1
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8.2. Register Description
8.2.1. Time/Calendar Counter Registers * In normal mode (CNTR = "0"), the counter is incremented by a write operation. (1) Second digit counter Counts values from 0 to 59. The counter can be read and incremented. When the second digit counter is incremented, fractions below full seconds are reset. Therefore a carry occurs 1 second after the increment operation is finished. A3 A2 A1 A0 Name D3 D2 D1 D0 Register contents 0 0 0 0 S1 S8 S4 S2 S1 1-second digit counter 10-second digit 0 0 0 1 S10 0 S40 S20 S10 counter (2) Minute digit counter A3 A2 A1 A0 Name D3 D2 D1 D0 0 0 1 0 MI1 mi8 mi4 mi2 mi1 0 0 1 1 MI10 0 mi40 mi20 mi10 Counts values from 0 to 59. The counter can be read and incremented. Register contents 1-minute digit counter 10-minute digit counter
(3) Hour digit counter A3 A2 A1 A0 Name D3 D2 D1 D0 Register contents 0 1 0 0 H1 h8 h4 h2 h1 1-minute digit counter 0 1 0 1 H10 PM/AM 0 h20 h10 10-minute digit counter Counts values from 0 to 23. The counter can be read, and the 1-hour digit counter can be incremented. (The 10-hour digit counter cannot be incremented.) D0 in the control register 1 sets the 12-hour/24-hour display format. 24/12 bit Displayed time 0 (12-hour format) AM 12:00 to AM 11:59, PM 12:00 to PM 11:59 1 (24-hour format) AM 00:00 to AM 11:59, PM 12:00 to PM 23:59 * PM/AM bit: This bit is output also when 24-hour format is selected. * Time keeping is not affected also when the 12-hour/24- hour format is switched during clock operation. (4) Day of the week digit counter A3 A2 A1 A0 Register contents Day of the week digit 0 1 1 0 W 0 w4 w2 w1 counter Counts values from 0 to 6. The counter can be read and incremented. The correspondence between count value and day of the week is set by the user. Example Data 0 1 2 3 4 5 6 Coded day of the week Sun. Mon. Tue. Wed. Thu. Fri. Sat. Name D3 D2 D1 D0
(5) Day digit counter A3 A2 A1 A0 Name D3 D2 D1 D0 Register contents 0 1 1 1 D1 d8 d4 d2 d1 1-day digit counter 1 0 0 0 D10 0 0 d20 d10 10-day digit counter The counter value is different depending on the month. (a) For long months (1, 3, 5, 7, 8, 10, 12), the counter counts values from 1 to 31. The counter can be read and incremented. (b) For short months (4, 6, 9, 11), the counter counts values from 1 to 30. The counter can be read and incremented. (c) For February, the counter counts values from 1 to 29 if it is a leap year and from 1 to 28 in other years. The counter can be read and incremented. (6) Month digit counter A3 A2 A1 A0 Name D3 D2 D1 D0 1 0 0 1 MO1 mo8 mo4 mo2 mo1 1 0 1 0 MO10 0 0 0 mo10 Counts values from 1 to 12. The counter can be read and incremented. Register contents 1-month digit counter 10-month digit counter
(7) Year digit counter A3 A2 A1 A0 Name D3 D2 D1 D0 Register contents 1 0 1 1 Y1 y8 y4 y2 y1 1-year digit counter 1 1 0 0 Y10 y80 y40 y20 y10 10-year digit counter Counts values from 0 to 99 for the last two digits of the year. The counter can be read and incremented. Until 2099, leap year compensation is automatically provided. ('92, '96, '00, '04, '08, '12, '16, '20 ... are leap years.)
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8.2.2. Control Registers (1) Control register 1 A3 A2 A1 A0 Name D3 D2 D1 D0 Register contents 1 1 0 1 CNT 1 TPS 30ADJ CNTR 24/12 Control register 1 Control register 1 performs 12-hour/24-hour display format switching, digit counter reset, 30 second adjustment, and timing pulse signal switching. The register allows data read and write. (a) TPS bit (D3) The TPS bit selects the timing pulse output waveform. TPS bit Frequency (cycle) "L" level duty 0 1024 Hz (976.5 s) 1/2 (488.28 s) 1 1/10 Hz (10 s) 3/5 (6 s) 1/10 Hz is not output for 10 seconds after power-on or system reset (output is "L"). (b) 30ADJ bit (D2) When "1" is written to this bit, one of the following reset operations is carried out. Seconds digit before Seconds digit after adjustment adjustment 29 seconds or less Seconds reset to "00" without carry to 1-minute digit 30 seconds or more Seconds reset to "00" with carry to 1-minute digit When "1" was written to the 30ADJ bit, the bit automatically resets itself to "0" within 76.3 s The 30 second adjustment function also resets fractions below full seconds. The TPOUT 1/10 Hz duty changes for one cycle only during 30 second adjustment. (c) CNTR bit (D1) The CNTR bit resets the time/calendar counters. CNTR bit Content 0 Normal mode (time/calendar counters can be incremented) 1 Selected counter is reset to "0" * For counters other than the year, selecting either the 1 or the 10 digit counter will reset both counters. When CNTR is used to reset the seconds, fractions below full seconds are also reset. The TPOUT 1/10 Hz duty changes for one cycle only during reset. (d) 24/12 bit (D0) The 24/12 bit serves to switch between 12-hour and 24-hour format. 24/12 bit Displayed time 0 (12-hour format) AM 12:00 to AM 11:59, PM 12:00 to PM 11:59 1 (24-hour format) AM 00:00 to AM 11:59, PM 12:00 to PM 23:59 * PM/AM bit: This bit is output also when 24-hour format is selected. * Time keeping is not affected also when the 12-hour/24- hour format is switched during clock operation.
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(2) Control register 2 A3 A2 A1 A0 Name D3 D2 D1 D0 1 1 1 0 CNT 2 BUSY PONC -- Control register 2 provides flags for carry detect and power-on-clear detect. Register contents Control register 2
(a) BUSY bit (D3) The BUSY bit serves for time/calendar counter digit carry detection. BUSY bit Mode Meaning 0 Normal mode Time/calendar counter read/write possible 1 Carry Time/calendar counter read/write prohibited If the BUSY bit is "L", carry does not occur for at least 3.9 ms. (Also when read/write is carried out at point "a" in the chart below, carry does not occur for 3.9 ms.) Take the processing time into consideration and design the read/write operation to complete within 3.8 ms. Clock read/write during carry * Read It may not be possible to read correct data. * Write Because the clock has priority, the write operation does not increment the counter. (During carry, the result is the same as for a read operation.)
BUSY timing
1s 3.9 ms
BUSY bit
Approx 0.5 s "a"
Carry pulse in IC Read/write possible Read/write prohibited (clock/calendar)
(b) PONC bit (D2) The PONC bit is the power-on-clear detection bit (see next page). It is set to "1" when power-on-clear is detected. The PONC bit is reset (1 0) by setting the SYSR bit to "1". (c) D1 bit (bit marked "--") When this bit is read, data are undefined. (d) D0 bit (bit marked " ") When writing this bit, always set it to "0".
(3) Control register 3 Control registers 3 serves for reading and writing data for address mode switching and making system reset settings. The control register 3 applies to modes 0 - 2. A3 A2 A1 A0 Name D3 D2 D1 D0 Register contents 1 1 1 1 CNT 3 SYSR TEST MS1 MS0 Control register 3 (a) SYSR bit (D3) The SYSR bit serves for clearing all counter registers (see section on initialization on next page). This bit is reset by making CS0 High and SCK Low. (b) TEST bit (D2) The TEST bit serves to switch the IC to the test mode. Note Be sure to permanently set this bit to "0". Otherwise correct operation is not assured. (c) MS1, MS0 bit (D1, D0) The MS1 and MS0 bits serve for address switching. MS1 MS0 Mode name Content 0 0 MODE 0 Time/calendar counters and control registers 1 - 3 0 1 MODE 0 Time/calendar counters and control registers 1 - 3 1 0 MODE 1 User RAM area (RA0 - RA59) and control register 3 1 1 MODE 2 User RAM area (RA60 - RA119) and control register 3
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8.3. How to use
8.3.1. Data Read When CS0 is "L", the serial address data input at SIN is read at the leading edge of SCK . Next, when
WR = "H" is taken in on the 8th pulse leading edge of SCK the counter control register or RAM address is selected. The data of the selected counter control register or RAM address are output in the following cycle from SOUT, in sync with the SCK trailing edge. 8.3.2. Data Write/Modify When CS0 is "L", the serial address data input at SIN is read at the leading edge of SCK . Next, when
WR = "H" is taken in on the 8th pulse leading edge of SCK , the counter control register or RAM address is selected, and data are written as shown below. Item Time/calendar Control register/RAM with the SCK trailing edge. Content Counter, counter data increment (+1) * Serial address/lower 4 bit of data are written
The selected counter register or RAM address data are output in the following cycle from SOUT, in sync * The hour digit counter can be incremented via the 1-hour digit counter. 8.3.3. Initialize (1) System reset When the SYSR bit in the control register 3 is set to "1", all logic bits are initialized. The SYSR bit is reset to "0" by causing an up transition of CS0 and a down transition of SCK . Register Time/calendar counters Control registers User RAM area Data year, 01-month, 01-day, AM 12-hour, 00-minute, 00- second, 0-day of the week All "0" (SYSR = "1") Undefined
Until system reset is released, TPOUT is fixed to "L". 1/10 Hz is not output for 10 seconds after system reset is released. (2) Power-on-clear At power-on, the power-on-clear function automatically performs a sequence identical to system reset. However, because the PONC bit remains at "1", a system reset must be performed to set the PONC bit to "0" before setting the time and calendar. 8.3.4. Timing Pulse Output The timing pulse is output from the TPOUT pin. Normally, a 1024 Hz signal is output. By setting the TPS bit in the control register 1 to "1", this can be switched to 1/10 Hz.
* Switchover timing
8th leading edge of SCK
SCK TPS
Approx 60 s Switch from 1024 Hz to 1/10 Hz
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RTC - 4553AC
8.3.5. Sample Operation Flow Charts (1) Time/calendar initialize example (Example for initialization through power-on-clear when battery was changed etc.) START SYSR 1 * Release PONC bit = "1" (1 0) * While BUSY = "1", a carry operation is in progress and the setting should not be carried out. The following processing steps must be completed within 996 ms after SYSR "1" or after the BUSY bit down transition was detected. If the process takes longer, the BUSY bit must be checked again for continued processing. * It is advisable to start the setting from the year digit, to prevent setting nonexistent data. * When the 1-digit of the year, month, day, hour, minute, or second is set, carry to the 10-digit can occur.
NO
BUSY = 0?
YES Increment 1-year digit and 10-year digit Increment 1-month digit and 10-month digit Increment 1-day digit and 10-day digit
Increment day of the week digit Set 24/12-hour format
* It is advisable to set this before setting the hour digit, to prevent setting nonexistent data. * Set the 10-hour digit by incrementing the 1-hour digit.
Increment 1-hour digit
Increment 1-minute digit and 10-minute digit
30ADJ 1 END
(2) Time/calendar modify example (8:00 12:00) START MS0=0, MS1=0
NO
BUSY = 0?
YES Increment 1-hour digit (4 times)
While BUSY = "1", a carry operation is in progress and the setting should not be carried out.
END
4 times (8 9 10 11 12) 10-hour digit is automatically carried. The processing should be completed within 3.8 ms after detecting BUSY = "0".
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RTC - 4553AC
(3) Time/calendar modify example using counter reset (8:00 2:00) (4) RAM write example
START
MS0="0", MS1="0"
START
MS0 0
NO
BUSY = 0?
YES CNTR 1 (80)
MS1 1
Set MODE 1
Write to RAM in MODE 1
MS0 1 MS1 1
Set MODE 2
Write hour digit
CNTR 0
Write to RAM in MODE 1
Increment 1-hour digit (2 times)
(012)
END
END
Note 1 Note 2 If processing is not completed within 3.8 ms, check the BUSY bit again. Reset (CNTR "1") applies to the digits for which writing was performed [1-hour digit and 10-hour digit in example (3)]. Consequently, to change the setting from 11:00 to 2:00, the hour digit must be reset (CNTR "1"). For the year, CNTR is used separately for the 1-year digit and 10-year digit. Performing CNTR on the 1-year digit does not change the 10-year digit. Conversely, performing CNTR on the 10-year digit does not change the 1-year digit. (6) RAM read example
(5) Time/calendar read example
START
MS0 0 MS1 0
START
MS0 0 MS1 0
PONC=0?
YES
NO
PONC=0?
NO
If PONC = "1", initialization was carried out and data must be set again
YES MS0 0 MS1 1
If PONC = "1", initialization was carried out and data must be set again Set MODE 1
NO
BUSY = 0?
YES Read time/calendar
If BUSY = "0", there will be no carry for at least 3.8 ms.
Read MODE 1 RAM
MS0 1 MS1 1
Set MODE 2
END
Read MODE 2 RAM
END
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RTC - 4553AC
(7) Time/calendar read example using BUSY bit down transition START
MS0 0 MS1 0
PONC=0?
NO
YES NO
If PONC = "1", initialization was carried out and data must be set again
BUSY = 1?
YES
NO
PONC=0?
Read time/calendar
Time and calendar read interval is 996 ms.
END
8.3.6. CS1 and CS0 Operation When designing a floating arrangement, take the following into consideration. CS0 can be floating while CS1 = "L", but CS1 can never be floating. (Otherwise a through current would flow, leading to increased current consumption during operation on backup battery power.) When CS1 = "L", input is disabled, and SOUT and TPOUT are at high impedance.
CS 1 CS 0 To internal circuits
To internal circuits WR To internal circuits
SIN
SCK SOUT
To internal circuits
From internal circuits
TPOUT
From internal circuits
8.3.7. System Power Down During Interface Operation When the system power goes down during interface operation with the CPU, causing CS1 to become "L", the incomplete data will be invalid. Immediately after system power restoration, when CS1 has become "H", the output data from SOUT are undefined for one cycle. 8.3.8. Power Supply and CS1 Operation When the system power is shut down, VDD falls to the battery voltage. When used at VDD 10%, CS1 must be set to "L" before VDD crosses point in the diagram below. When system power is restored, CS1 must be set to "H" before VDD crosses point . System power on/off time chart
System power
VDD
VDD-20 %
5V Battery voltage
CS1
Access disabled Power down
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RTC - 4553AC
8.3.9. Power-On Reset When the system power is turned on, the power-on reset function operates automatically, performing a sequence identical to system reset. However, because the PONC bit remains at "1", a system reset must be performed to set the PONC bit to "0" before setting the time and calendar. The conditions for power-on reset and the conditions for data retention and normal IC operation during power fluctuation are shown below.
VDD [V] 5 4 3 2 1 0 t t1 t2
Ta = -30 C to +70 C t1 t2 Note 1 Note 2 Condition tR for power-on reset +0.3 +0.3 at 0 V 3 V or 0 V5V Condition tR for no power-on reset at 2 V 3 V or 2 V 5 V (Note 1) (Note 2) 1.0 s/V tR 1.6 ms/V 1.0 s/V tR 1.6 ms/V
Note: 3 V and 5 V are recommended voltages. 2 V is the backup voltage. t1: Condition for power-on reset t2: Condition for data retention and normal IC operation during power-on
The voltage level before initial power-on should be 0.3 V or less. If powering up from an intermediate potential, power-on reset may not be performed correctly. Be sure to verify correct operation. Within the voltage range for data retention and clock operation (2.0 V - 5.5 V), power-on reset is designed not to be performed under the above conditions, to prevent data loss. When the voltage level falls below 2 V, operation and data retention are no longer assured. During power-on or power restoration from an intermediate potential outside of the assured operation range (0.3 V - 1.9 V), the power-on reset circuit will not operate normally, leading to possible malfunction. If the backup battery voltage has fallen below 2.0 V, the VDD pin of the RTC must be temporarily set to ground potential before restoring the power.
Note 3
8.3.10. Power Supply Connection Example
+5 V +VCE +5 V RTC VDD R
Power-down detection circuit
+ CS1 + GND
0.1 F
Use a high capacitance value here to guard against reverse current flowing from the collector to the emitter of the transistor during transition from power on to power off.
Secondary battery or lithium battery. (Lithium battery requires the diode shown in . Regarding the value of the resistor R, consult the battery manufacturer.
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RTC - 4553AC
8.3.11. Processing of Non-Existent Data (1) If the month digit is incremented while the current setting is January 31, a non-existent setting will result (February 31). Carry from the hour digit will cause this setting to become March 1.
Month digit incremented Carry from hour digit
Jan. 31
Feb. 31
Mar. 01
(2) If the year digit is incremented while the current setting is February 29 of a leap year, a non-existent setting will result (February 29 of a non-leap year). Carry from the hour digit will cause this setting to become March 1.
Year digit incremented Carry from hour digit
Feb. 29
00
Feb. 29
01
Mar. 01
01
When the following non-existent data are set (February 30), incrementing the 10-day digit causes an overflow in the 10-day digit, clearing the 1-day digit.
10-day digit incremented once 10-day digit incremented once
Feb. 30 Feb. 29
Feb. 00 Feb. 01
Feb. 10
When a valid date is set, overflow of the 10-day digit does not clear the 1-day digit. (3) When the 10-day digit is incremented past "31", the day digit counter becomes "01". (4) When the 10-month digit is incremented, the month digit overflow processing will differ according to the month.
10-month digit incremented once
Non-existent month
00 month
Oct.
Oct.
00 month
Non-existent month
Nov. Dec. Mar. - Sep.
Jan. Feb. Jan.
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RTC - 4553AC
8.3.12. Timing Charts (1) Data readout example
WR
CSo
SCK
SIN
Don't care
A0
A1
A2
A3
Don't care
a0
a1
a2
a3
Don't care
1-second digit address (0000)
Next address (10-second digit) (0001)
SOUT
: Undefined
A*
A*
A*
A*
D*
D*
D*
D*
A0
A1
A2
A3
D0 D1
D2
D3
Previously accessed address and data
1-second digit address (0000)
1-second digit data
When specifying the next data read access, the previously accessed address and data appear at SOUT. Same applies for reading from SRAM. SIN : Input at leading edge of SCK SOUT : Output at trailing edge of SCK
(2) Continuous data readout example
WR
CSo
SCK
SIN
Don't care
Address
Don't care
Address
Don't care
Address
Don't care
Access 1 (1-second digit)
Access 2 (10-second digit)
Access 3 (1-minute digit)
SOUT
: Undefined
Address
Data
Address
Data
Address
Data
Previously accessed address and data
1-second digit contents
10-second digit contents
When specifying the next data read access, the previously accessed address and data appear at SOUT. SIN : Input at leading edge of SCK
SOUT : Output at trailing edge of SCK
Additional information * When CS0 is "L", the serial address data input at SIN are read at the leading edge of SCK . Next, when WR = "H" is taken in on the 8th pulse leading edge of SCK , the counter control register or RAM address is selected, and the data from the selected counter control register or RAM address are output from SOUT in sync with the trailing edge of SCK . * When the SCK clock is less than 8 pulses, the module enters the command standby mode. When the SCK clock is more than 8 pulses, the command is not input correctly. The internal SCK clock counter is cleared at the leading edge of CS0 .
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RTC - 4553AC
(3) Time/calendar continuous write example (CNTR=0)
WR
CSo
SCK
SIN
Don't care
Address
Don't care
Address
Don't care
Address
Don't care
Access 1 (1-second digit)
Access 2 (10-second digit)
Access 3 (1-minute digit)
SOUT
: Undefined
Address
Data
Address
Data
Address
Data
Previously accessed address and data
1-second digit contents + 1
10-second digit contents + 1
The write result appears at SOUT when specifying the next access. When wanting to check the write result, it is therefore necessary to specify another read or write operation. (When using write access, note that the data of that address will be further incremented by 1.) For continuous write operations, the CS0 must be kept "L" for the required number of increments (+1). SIN : Input at leading edge of SCK
SOUT : Output at trailing edge of SCK
(4) SRAM data write example
WR
CSo
SCK
SIN
Don't care
A0
A1 A2
A3 D0 D1 D2
D3
a0
a1
a2
a3
d0
d1
d2
d3
SRAM address (0000)
Data to be written (1111)
Next SRAM address (0001)
SOUT
: Undefined
A*
A*
A*
A*
D*
D*
D*
D*
A0 A1
A2 A3 D0 D1 D2 D3
Previously accessed address and data
SRAM address (0000)
Data to be written to SRAM (1111)
The write result appears at SOUT when specifying the next access. When wanting to check the write result, it is therefore necessary to specify another read or write operation. SIN data are valid only during SRAM write access. SIN : Input at leading edge of SCK
SOUT : Output at trailing edge of SCK
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RTC - 4553AC
Additional information When CS0 is "L", the serial address data input at SIN are read at the leading edge of SCK . Next, when WR = "H" is taken in on the 8th pulse leading edge of SCK ., the counter control register or RAM address is selected, and data are written as shown below. Counter data are incremented. Example Time/calendar (CNTR = "0")
Data before incrementing 0 8 Number of incrementing steps 4 3 Data after incrementing 4 11 (10-digit is carried automatically.)
Control register and SRAM Address and 4-bit data are written. The selected counter register or RAM address data are output in the following cycle from SOUT, in sync with the SCK trailing edge. (5) System reset The SYSR (system reset) condition can be released by causing an up transition of CS0 and a down transition of SCK .
WR
CSo
SCK
SIN
Don't care
A0
A1
A2
A3
D0 D1 D2
D3
Don't care
Don't care
Address (1111)
Data (0111)
SYSR bit
System reset
Release
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MQ - 342 - 01
RTC - 4553AC 9. External dimensions / Marking layout
9.1. External dimensions RTC - 4553 ( SOP-14pin )
* External dimensions 10.1 0.2
#14 #8
* Recommended soldering pattern 0 - 10 1.4
5.0
7.4 0.2
5.4
0.6
#1 #7
1.4
0.15 0.05 Min. 1.27 0.7 1.27 x 6 = 7.62
3.2 0.1
0.35
1.27
1.2
Unit : mm
9.2. Marking layout RTC - 4553AC ( SOP-14pin )
Model identifier
Frequency tolerance indication
R4553 AC E
Symbol mark
Indication AC
1234A
Frequency tolerance 5 x 10-6
Production lot
Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning.
Page - 21
MQ - 342 - 01
RTC - 4553AC 10. Reference Data
(1) Frequency/temperature characteristics
x 10
0
-6
[Calculating the frequency stability] 1. Frequency/temperature characteristics are approximated according to the following equation. 2 fT = (T - X) : Frequency tolerance at given fT temperature 2 : Secondary temperature (1 / C ) coefficient -6 2 ((-0.0350.005) x 10 / C ) : Peak temperature (+25C 5C) T (C) : Given temperature X (C)
100
T = +25 C Typ. -6 = -0.035 x 10 Typ.
Frequency fT
-50
-100
-150 -50
0
50
Temperature [C]
2. To calculate the clock accuracy, add the frequency tolerance and voltage characteristics f/f = f/fo + fT + fV : Clock accuracy at given f/f temperature and voltage (frequency stability) : Frequency tolerance f/fo : Frequency deviation at given fT temperature : Frequency deviation at given fV voltage 3. Calculating the daily deviation Daily deviation = f/f 86400 (seconds) -6 * For example, at f/f = 11.574 10 , the deviation is about 1 second per day.
(2) Frequency/voltage characteristics example
(3) Current consumption/voltage characteristics example
x 10
-6
Condition : +4 +2 0 -2 2 -4 3 4 5 6 Current consumption [ A ] 5 V as reference, Ta= +25 C Condition : 2 Ta = +25 C , CS1 = 0 V
Frequency fv
1
Supply Voltage VDD [ V ] 2 3 4 5 6
Supply Voltage VDD [ V ]
Note
These data are reference values for the sample lot.
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MQ - 342 - 01
RTC - 4553AC 11. Application notes
11.1. Notes on handling
This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling. (1) Static electricity While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials. In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used with this module, which should also be grounded when such devices are being used. (2) Noise If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up." In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1 F as close as possible to the power supply pins ( between VDD and GND ). Also, avoid placing any device that generates high level of electronic noise near this module. Do not connect signal lines to the shaded area in the figure shown in Fig.1 and, if possible, embed this area in a GND land. (3) Voltage levels of input pins When the input pins are at the mid-level, this will cause increased current consumption and a reduced noise margin, and can impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VDD or GND. (4) Handling of unused pins Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit state can lead to unstable voltage level and malfunctions due to noise. Therefore, pull-up or pull-down resistors should be provided for all unused input pins. ( except L1-L5 pins )
11.2. Notes on packaging
(1) Soldering temperature conditions If the temperature within the package exceeds +260 C, the characteristics of the crystal oscillator will be degraded and it may be damaged. Therefore, always check the mounting temperature before mounting this device. Also, check again if the mounting conditions are later changed. See Fig.2 for the soldering conditions of SMD products. (2) Mounting equipment While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the mounting conditions are later changed, the same check should be performed again. (3) Ultrasonic cleaning Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time, state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic cleaning. (4) Mounting orientation This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before mounting. (5) Leakage between pins Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the device is dry and clean before supplying power to it. Fig. 1: Example GND Pattern RTC - 4553
( SOP-14pin )
Fig. 2: Soldering Conditions of SMD Products Air Reflow Profile
Temperature[ C ] +240 C Max. +235 C 5 C +200 C 10 s 1 s
+150 C 10 C
90 s 30 s
30 s 10 s Time[ s ]
Page - 23
MQ - 342 - 01
Application Manual
Distributor
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